Planar junctionless poly-Si thin-film transistors with single gate and double gate

In this letter, single- and double-gate (SG and DG) planar junctionless (JL) thin-film transistors fabricated via a simple process with an in situ-doped active layer is discussed. The DG structure demonstrated a superior subthreshold swing of 160 mV/dec and a lower off-current of 1.3 × 10 −13 A than those of 329 mV/dec and 2.1 × 10 −12 A for the SG structure, respectively. It contributes to the enhancement of the gate controllability and ultrathin channel. Consequently, the simple fabrication process of the DG JL device is suitable for future application on system-on-panel and three-dimensional integrated circuits.