A low-power 128-tap digital adaptive equalizer for broadband modems

This paper describes a modem receiver chip containing two 64-tap adaptive finite impulse response (FIR) filters configured in parallel as in-phase and quadrature-phase filters. Each filter has a span of 16 symbols and can be configured for T/2, T/3, or T/4 fractional spacing. A zero-latency pipeline technique is used that allows adaptive filters of arbitrary length without degrading the speed. Power is saved at the algorithmic, architectural, and circuit levels. The chip has support for dynamically tuning coefficient precision, updating rates and filter lengths to reduce power consumption. The chip was fabricated in 0.5-/spl mu/m CMOS technology and consumes 535 mW of power when operating at 50 MHz with 128 taps, T/4 spacing, and symbol-rate power-of-two LMS updating. This can be further reduced to 280 mW using dynamic power reduction techniques. The power in the FIR filter is 162 mW with maximum precision converged coefficients which corresponds to 5.1 mW per multiply-accumulate operation.