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Carrier phase offset tracking, a crucial operation in analog signal processing-based coherent receivers, aims at the measurement and correction of the time-varying phase offset in the received signal and enables reliable data recovery. In this work, we present system-level integration, analysis, along with measurement setup and results of an all electrical Costas loop (AECL)-based carrier phase recovery and compensation (CPRC) in carrier-forwarded coherent data center interconnect (DCI) links. Major constituents of AECL—a single sideband mixer, a phase detector (constituents of carrier phase synchronization chip), and a quadrature-phase voltage-controlled oscillator (realized using discrete electrical components)—are characterized independently. These components, when integrated on system level in an optimized feedback loop manner with other loop components, are shown to correct the phase offset between modulated signal and forwarded carrier in carrier-forwarded DCI links. The experimental measurement setup and results are presented for carrier-forwarded QPSK link that can be extended to higher order modulation and polarization diverse schemes for 400Gb/s/λ(and beyond) coherent-lite DCIs.
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Ashok et al. (2023) studied this question.
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