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Despite recent advances in the speed of digital computers and in numerical algorithms for the solution of differential equations, the evaluation of the dynamic response of nonlinear circuits is still too slow to permit Monte Carlo tolerance analysis. However, the performance of many nonlinear circuits can be evaluated on a static basis. One example is a D/A converter built with devices much faster than the converter's cycle time. Algorithms now exist that produce the static or equilibrium solution of such networks in seconds. This paper deals with these algorithms and the associated techniques that have been embodied in a program for the Monte Carlo tolerance analysis of nonlinear, “dc,” circuits.
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Cermak et al. (1971) studied this question.
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