Two-dimensional transient analysis of a collector-up ECL inverter

For very small-geometry devices, two-dimensional parasitic effects can be complicated and models with extracted parameters may not be sufficient for accurately analyzing circuit performance. Using a device-level simulator, PISCES-2B, with appropriate boundary conditions, the transient performance of an emitter coupled logic (ECL) inverter with collector-up bipolar transistors of 1 mu m*1 mu m has been analyzed. The propagation delay of this inverter is less than 30 ps for driving an output load of 2 fF with an output swing of 0.8 V at a biasing current of 120 mu A. The speed performance is the result of its buried common emitter structure and its very small collector-to-substrate parasitic capacitances.>