Low leakage current Cu(Ti)/SiO2 interconnection scheme with a self-formed TiOx diffusion barrier

Electrical and material properties of Cu(0.02 wt % Ti) alloy and pure Cu films deposited on SiO2/Si are explored. Current–voltage measurement using metal–oxide–semiconductor (MOS) capacitor structure reveals low leakage current (10−8 A/cm2) for capacitors with as-deposited Cu(0.02 wt % Ti) and pure Cu metal gates. However, after annealing at 700 °C in a vacuum, leakage current of MOS capacitors using a pure Cu gate shows a dramatic rise of leakage current at a low electrical field, while the leakage current of capacitors with Cu(0.02 wt % Ti) gate stays at ∼10−7 A/cm2. Concurrently, the resistivity of annealed Cu(0.02 wt % Ti) is reduced to 2.5 μΩ cm, which is only slightly greater than the resistivity of as-sputtered pure Cu films. X-ray photoelectron spectroscopy indicates that a TiOx layer has formed at the Cu(0.02 wt % Ti)/SiO2 interface after annealing and Auger electron spectrometry depth profiles show less interdiffusion at the Cu(0.02 wt % Ti)/SiO2 interface than the Cu/SiO2 interface. The correlation between leakage current reliability and the interfacial reaction upon annealing is discussed.