Fermi-level position at a semiconductor-metal interface

We have investigated the phenomenon of Fermi-level pinning by charged defects at the semiconductor-metal interface. Two limiting cases were investigated. In the first case we modeled an infinitely thick metallic coverage. In the second case we modeled a submonolayer coverage by using a free semiconductor surface containing defects. In both cases we assumed that most of the defect-induced interface states are localized inside the semiconductor, not more than a few angstroms away from the metal. Under these conditions we have estimated the difference in Fermi-level position between n- and p-type semiconductors to be less than 0.05 eV in the case of a thick metallic coverage. This difference was shown to be the maximum possible one, and it occurs only when there is no pinning. When there is pinning, this difference is even smaller. No such upper bound on the difference in Fermi-level position exists in the case of submonolayer coverage. We have also found that the defect density required to pin the Fermi level is {~}10¹⁴ cm^-2 in the case of a thick metallic coverage, but only {~}10¹² cm^-2 in the case of a submonolayer coverage.