Design methodology of clock signal manipulation detectors in FPGAs and ASICs to strengthen vulnerable cryptosystems against fault injection

The growth of the secure Internet of Things has led, among other aspects, to the necessity of ensuring the confidentiality of sensitive user data while simultaneously adhering to stringent constraints regarding area and resource consumption. Attacks on physical implementations of cryptographic primitives are numerous and increasingly sophisticated, making the development of secure crypto-systems a challenge. This paper presents a methodology for designing a lightweight detection scheme for detecting fault injections by clock manipulation in hardware-oriented information encryption algorithms in both FPGAs and ASICs. To demonstrate its versatility and fault coverage, several experimental tests have been performed on an Artix-7 100T FPGA and a TSMC 90nm ASIC that incorporate the proposed schemes on both the standard AES block cipher and the standard Trivium stream cipher. Furthermore, its use against electromagnetic attacks has been evaluated. The experimental results on both technologies show that the scheme is able to detect 100% of both the clock signal manipulation and electromagnetic attacks, with a negligible penalty in area consumption and without frequency degradation.