A 15T SRAM Cell-Based Fully-Digital Computing-in-Memory Macro Supporting High Parallelism and Fine-Grained Simultaneous Read + Write + MAC Operations

A 15-transistor (15T) SRAM cell based fully-digital CIM macro is proposed for AI accelerations. The CIM macro not only supports simultaneous read + write + MAC operations, but also supports ultra-wide-range voltage scaling, digital design flow, and cell-wise bit interleaving. A fine-grained weight update scheme is introduced to perform write and MAC operations simultaneously. A specialized twos complement processing strategy is proposed to enable efficient signed MAC operations without sign extension. Fabricated in a 55-nm CMOS technology, the proposed fully-digital CIM macro enhances the peak energy efficiency by up to 3.46W compared with the state-of-the-art digital CIM schemes.