A broadband 64*16 space-switching approach and its applicability to large-scale broadband switching systems are described. The design uses a technique that prevents the parasitic capacitances from reducing the switching speed. The switching system was implemented in 3- mu m CMOS VLSI and operated in excess of 150 Mb/s. Computer simulation indicates a 1-Gb/s potential with a 1- mu m CMOS implementation.>
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Cooperman et al. (1989) studied this question.
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