Modeling of ADC-Based Serial Link Receivers With Embedded and Digital Equalization

Serial link receivers with high-speed analog-to-digital converters (ADCs) can utilize powerful digital-domain equalizers and support multilevel modulation schemes. This paper presents a hybrid statistical modeling framework for ADC-based serial link receivers. The framework builds upon the existing statistical modeling techniques for mixed-signal receivers and adds the support of ADC quantization noise, radix errors [integral nonlinearity and differential nonlinearity (INL/DNL)], and time-interleaving mismatches. A rapid purely statistical simulation mode is utilized to model systems with small front-end nonlinearity and ADC INL/DNL. To include ADC INL/DNL, a hybrid approach is presented with an initial short transient simulation. The presented modeling framework is used to explore the effectiveness of embedding an analog feed-forward equalizer (FFE) in the ADC of a 10-Gb/s receiver. Measurement results of a 10-Gb/s ADC-based receiver prototype with a three-tap embedded FFE in the ADC and a digital four-tap FFE and three-tap decision feedback equalizer are presented to validate the presented framework.