A PWM and PAM Signaling Hybrid Technology for Serial-Link Transceivers

A 1-Gb/s 0.18- mum CMOS serial-link transceiver using multilevel pulse-width and pulse-amplitude modulation (PWAM) signaling and a pre-emphasis technique is presented. Based on the PWAM technique, the transmit signaling is implemented to effectively push high data rates through bandwidth- limited channels. The clock is implicitly embedded in the 4-bit data stream, and the associated overhead needed in the clock-and-data recovery circuitry can be mitigated. In addition, the pin count can be reduced by transferring the data channels and the clock channel over a single transmitted channel. The recovered clock has an rms jitter of 5.9 ps at 250 MHz, and the retimed data have an rms jitter of 13.7 ps at 250 Mb/s. The occupied die area is 1.65 X 1.40 mm2. The transmitter and receiver power consumption is 86 and 45 mW, respectively.