Threshold-sensitivity minimization of short-channel MOSFET's by computer simulation

This paper describes an approach to reducing short-channel effects in small-dimension MOSFET's, with emphasis focused on the geometrical channel structure along a gate. To minimize threshold-voltage sensitivities, the advantage of an inhomogeneous channel structure with a highly doped region near the source is demonstrated through a theoretical analysis and extensive use of a two-dimensional device simulation. This structure, which can be realized through DSA technology, obtains adequate tolerances for both the channel length and applied drain voltage in the 1-µm channel-length MOSFET; the anticipated channel-length tolerance (Δ L) for maintaining the threshold-voltage fluctuation to within ± 10 percent is estimated to be ± 0.25 µm whenVd = 5.0V and gate-oxide thicknesstₒₓ = 30nm. With this tolerance, threshold sensitivity to drain voltage drops to one-third in a conventional MOSFET. In a 0.5-µm channel-length MOSFET, (Δ L) is estimated to be ± 0.7 µm whenVd= 3.0V.