Junctionless nanowire transistors (JNTs) have been fabricated on ultra-thin-body germanium-on-insulator (GOI) substrates using a simple Si-compatible top-down process. These JNTs, which have gate lengths and widths that are both less than 100 nm, exhibit good electrical characteristics (Ion/Ioff ratio of ∼105 at Vd = −1 V). The effects of the back gate voltage, temperature, the device dimensions, and the channel doping concentration on the leakage currents of the fabricated devices were experimentally analyzed in detail. The results indicate that the leakage current is mainly affected by the gate tunneling current, the Shockley-Read-Hall generation current, the band-to-band tunneling current and the trap-assisted tunneling current. Design guidelines were then proposed to reduce the leakage currents of GOI-based JNTs.
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Sun et al. (2015) studied this question.
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