High-Performance Voltage-Fed AC–DC Full-Bridge Single-Stage Power Factor Correctors with a Reduced DC Bus Capacitor

Full-bridge single-stage (FBSS) ac-dc converters allow to regulate both the output voltage and the input current that achieves a near sinusoidal waveform using only the four bridge transistors. Independent of this feature, these converters still need to be optimized in order to become an interesting and attractive solution for modern switch mode power supplies with power factor corrector (PFC) function. One of the most important improvements needed is the downsizing of the dc bus capacitor C b with the inherent cost reduction. However, this action introduces complex issues in the regulation of the input current and it is also responsible for the generation of high output voltage ripple. The new contribution of this paper consists in the introduction of a set of power circuit optimizations and control techniques in a FBSS PFC converter that solves the referred issues in order to enable the reduction of the dc bus capacitor's size and cost. These procedures are based in the use of a free wheeling circuit that improves the light load operation and in the application of one shot nonlinear modulator, in order reduce the output voltage ripple even when the dc bus ripple is high. The possibility of using, in the proposed topology, a reduced ratio capacitance/watt lower than the typical values used in commercial applications (0.7-0.5 μF/W for 385-450 V, respectively), while maintaining the accurate input current regulation, is also theoretically proved. The developed concepts, solutions and design criteria are detailed described in the paper. The correspondent theoretical study is verified trough experimental results token in an optimized FBSS topology prototype.