This paper reports on the analytical approach for designing field plates for reducing the electric field in the channel and at the surface of heterostructure field-effect transistors (HFETs) for a given drain voltage, with the smallest possible increase of the gate capacitance. The analytical calculations for GaN-based HFETs are in good agreement with the two-dimensional numerical simulations.
No takes yet. Share an insight, caveat, or question.
Karmalkar et al. (2005) studied this question.