Switching time limits of loaded OR/AND RCJL Josephson logic gates

We have investigated by computer simulation the performances of loaded OR/AND RCJL logic gates with fan in/fan out (2 or 3) and picosecond Josephson Junctions (RNC ≥ 2 ps). We propose new gate structures designed to have small turn on delay and taking the best advantage of fast Junctions. The shunt on the input Junction responsible of long t.o.d, is eliminated. The static and dynamic operation of the gates are analyzed to operate with moderate overdrive (20%), 25% static margins, low power dissipation in the sub-ten-picosecond range using available technology.