11 2009 3212 3223 5308589 10.1109/JSSC.2009.2030050 http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=5308589 <![CDATA[A 10-Bit 500-MS/s 55-mW CMOS ADC

A pipelined ADC incorporates a digital foreground calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a highspeed, low-power op amp topology and an accurate on-chip resistor ladder and designed in 90-nm CMOS technology, the ADC achieves a DNL of 0.4 LSB and an INL of 1LSB. The prototype digitizes a 233-MHz input with 53-dB SNDR while consuming 55 mW from a 1.2-V supply.