Deuterium transport through device structures

We use secondary ion mass spectrometry to characterize the hydrogen/deuterium distribution and concentration on complimentary “metal” oxide silicon (CMOS) test structures subjected to molecular deuterium (D2) anneals. We examine the temperature dependence and the influence of doping on the transport of deuterium to the gate oxide interfaces resulting in interface passivation. We find that undoped polycrystalline silicon appears to be an efficient barrier for deuterium transport at typical postmetallization sintering temperatures. We also examine the permeability of device structures that include dielectric encapsulation layers after typical postmetal sintering conditions employed in a conventional CMOS process flow. It is found that typical low temperature deposited oxide dielectrics are quite permeable by molecular deuterium at typical sintering temperatures (435 °C). In contrast, chemical vapor deposited silicon nitride dielectrics appear to form a complete barrier to deuterium diffusion (even for layers as thin as 300 Å). We also find that nitrides which receive a high thermal budget exposure, such as the source/drain anneal, appears to regain permeability to deuterium diffusion/transport.