Systematic method for synthesising purely delay-insensitive circuits

A novel model for specifying a delay-insensitive circuit is introduced, in which transition signals and two-phase communication convention are used. In this model, a circuit is described by various states. At each state, an input to the circuit not only produces an output, but also causes a corresponding state transition. Based on this model, a systematic method for synthesising purely delay-insensitive circuits is presented, which is suitable for the design of control, data transmission and data-processing circuits.