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In this paper, the performance and the gate bias stability of amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) with different channel sputtering conditions, RF and DC are studied. DC devices show excellent electrical characteristics but larger charge trapping and slower detrapping in relaxation period under the same gate bias stress. To understand the cause of stress behavior, traps are extracted by subthreshold slop and low-high frequency dependent capacitance measurement and compared before and after gate bias stress. The extracted trap densities well explain the process-dependent device properties like as threshold voltage, mobility and on/off current ratio, but are not dependent on bias stress. From current–voltage (I–V) and capacitance–voltage (C–V) measurement, we can conclude that the threshold voltage instability arises due to the process of temporary charge trapping which is dominant only at gate bias stress and the trapping/detrapping behavior is strongly dependent on the channel layer deposition condition.
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Park et al. (2009) studied this question.
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