Local resistance measurement across grain boundaries in low-temperature polycrystalline silicon layer of thin film transistor using scanning spreading resistance microscopy

Local resistance distribution in a low-temperature polycrystalline Si layer of a thin film transistor with a lightly doped drain (LDD) structure was investigated using scanning spreading resistance microscopy. The local resistance around the grain boundaries was found to be lower than that at grain insides in the drain, LDD, and channel regions. At the center of the grain boundaries, however, slightly higher resistance part was sandwiched between low resistance regions. Identifying the drain, the LDD, and the channel regions is succeeded by an analysis in which only the lower local resistances were used.