A 64Kb × 32 DRAM for graphics applications

A high-speed 2Mb CMOS DRAM with 32 data I/Os is described. A 0.6-µm CMOS process with a single polysilicon layer, two levels of metal, and substrate-plate trench-capacitor (SPT) memory cells is used to fabricate the chip. It is designed to provide the wide data bandwidth required by high-performance graphics applications. A 35-ns access time with an 80-ns cycle time has been demonstrated. The 32-bit data bus and the high-speed feature achieve more than two times better graphics performance than conventional dual-port memories. A sensing method with a 2/3 VDD bit-line precharge voltage and a limited bit-line voltage swing is exploited to optimize speed and power. The chip, which operates on a 5-V power supply, dissipates 140 mA at the 80-ns cycle time.