An injection-locked delay line oscillator multiplies a 5-6-GHz input by 3 to generate I/Q LO signals for 17-GHz wireless networking applications. I/Q errors caused by asymmetric injection are minimized by symmetric injection via a passive polyphase prefilter. Passive delay lines set the measured free-running frequency of the LC ring oscillator to 16.24 GHz. The measured locking range for a 0 dBm (50 /spl Omega/) input is 14.6-17.86 GHz. Input-to-output phase noise degradation is negligible, and I/Q amplitude and phase errors are <0.17 dB and <2/spl deg/, respectively. Power consumption of the 1.2/spl times/1.4 mm/sup 2/ 0.2 /spl mu/m SiGe BiCMOS testchip (excluding buffers) is 22 mW at 2.2 V.
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Ma et al. (2004) studied this question.
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