Effect of III/V-Compound Epitaxy on Si Metal-Oxide-Semiconductor Circuits

Several approaches to the heteroepitaxial growth of InP on (100)Si employing an electrochemically etched Si mesa, SiO2 masks, and a maskless procedure were investigated with the objective of achieving area-selective InP integration into Si metal-oxide-semiconductor (Si-MOS) technology. Maskless InP/Si device layer growth by metal-organic vapour-phase epitaxy with good selectivity on a structured InP buffer layer, surrounded by oxide, was achieved. Undesired InP depositions were removed with an SiO2 emulsion, spun on prior to InP growth. To study the effects on the Si-based electronics, p-metal-oxide-semiconductor field-effect tansistors (MOSFETs) were exposed to the various stages of the heteroepitaxial InP growth process. We have studied the influence of hydride atmospheres and thermal anneals on their electrical performance. A standard InP-on-(100)Si growth procedure was found to be acceptable for the MOS components, as demonstrated by a Schmitt-trigger laser-diode driver circuit.