Quaternary voltage-mode CMOS circuits for multiple-valued logic

A set of novel voltage-mode CMOS circuits for the implementation of multiple-valued logic (MVL) systems is introduced. The circuit level implementation of the multiple-valued logic operators: logical sum, logical product, level-up, level-down and level conversions are presented. The mathematical properties of the latter operator are formally proved. The proposed multiple-valued logic circuits exhibit zero static power consumption, do not use clocking, and function on any arithmetic base. The proposed circuits consist of appropriately constructed enhancement-mode and depletion-mode 1.5 µm MOSFETs. Simulation of the introduced quaternary logic voltage-mode CMOS circuits, using SPICE, indicates improved performance (higher speeds) compared to existing ones.