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A novel CMOS low-voltage output stage is proposed. It is based on a class AB common source configuration with improved efficiency in terms of drive capability compared with silicon area. It provides a drive capability which is greater than the previous solution by a factor of 2 with the same aspect ratios and the same quiescent current. A 2 mA peak-to-peak output current is achieved with a 1.2 µm CMOS process, a 1.2 V power supply and a maximum output transistor aspect ratio of 375/1.2. The output stage is also well controlled under bias conditions, and hence standby power dissipation, frequency response and small signal linearity are all well defined.
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G. Palumbo (1999) studied this question.
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