A broad-band power divider is presented in CMOS technology. The devices are realized by postprocessing chips that are fabricated in a standard 1.2-μm CMOS process. Developed postprocessing includes wire bonding for ground equalization, deposition of a stress-compensation layer, and selective etching of the silicon substrate. By employing coupled coplanar transmission lines, the area of dividers is minimized to 0.8 mm×2.1 mm. A 20-35 GHz power divider exhibits a coupling of -3.8 dB/spl plusmn/0.6 dB.
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Ozgur et al. (2000) studied this question.
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