Analysis of admittance measurements of MOS capacitors on CVD grown bilayer MoS 2

In this study we present results on the AC admittance response of bilayer MoS 2 films grown using chemical vapor deposition. A new MOS capacitor design for ultra-thin body 2D materials is proposed. We show that along with the density of interface traps ( D it ), a transverse electric field distribution in the semiconductor and parasitic capacitance also cause frequency dispersion in measured capacitance. D it extracted using the conductance method in 40 devices indicates reliable measurements for channel length, L < 10 m. For devices with L > 10 m, an increase in D it is an artifact of access resistance in the semiconductor. Temperature measurements show an increasing defect distribution from cm −2 eV −1 around mid-gap to cm −2 eV −1 close to the conduction band minimum.