A ferroelectric semiconductor floating-gate transistor based on van der Waals heterostructures

With the explosive expansion of information, there is a growing need for non-volatile memories with high storage density and reconfigurability. Emerging two-dimensional (2D) ferroelectric materials enable the design of various high-performance functional devices that can potentially address these challenges. Here we report a ferroelectric semiconductor floating-gate transistor based on an α-In2Se3/h-BN/multi-layered graphene (MLG) van der Waals heterostructure on a SiO2/Si substrate. Thanks to the coexistence of both out-of-plane and in-plane polarizations in an α-In2Se3 channel, pairs of polarization-modulated channel resistance states can be successfully generated between the floating-gate-modulated on and off states, which can be programmed by either vertical gate pulses or planar drain pulses. These features enable a 2-bit multi-level memory in both three-terminal or two-terminal operational modes, significantly increasing the storage density and reconfigurability. The present results introduce a new design degree of freedom for floating-gate memories and provide fresh insights into future non-volatile memory technologies.