Successive Conformal Mapping Technique to Extract Inner Fringe Capacitance of Underlap DG-FinFET and Its Variations With Geometrical Parameters

We propose a new analytical model based on successive conformal mapping to compute the bias dependent inner fringe capacitance in nonplanar multigate MOSFET structure with doping modulated source/drain (S/D) and gate underlap for sub 20-nm node. The conventional analytical model of capacitance and resistance for planar MOSFET cannot be applied to the nonplanar multigate MOSFET. This model considers 3-D devices fabricated on bulk oxide, gate-S/D extension with nonuniform doping gradient and spacers. The percentage variation of inner fringe capacitance with respect to underlap length is studied for various fin width and oxide thickness.