Bulk Inversion in FinFETs and Implied Insights on Effective Gate Width

Relative values of on-state current in undoped-body double-gate (DG) and triple-gate (TG) FinFETs are examined via three-dimensional numerical device simulations. The simulation results reveal significant bulk inversion in the fin bodies, which limits the benefit of the third (top) gate in the TG FinFET and which negates the utility of the commonly defined effective gate width (W/sub eff/=2h/sub Si/+w/sub Si/). Even the concept of W/sub eff/ for the TG FinFET is invalidated, but the proper W/sub eff/ for the DG FinFET is defined. Physical insights attained from the simulations further solidify our notion, based previously on gate layout-area inefficiency, that the third gate is neither desirable nor beneficial.