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Thermal processing of polycrystalline silicon (polysilicon)/SiO2/SiC metal-oxide-semiconductor (MOS) devices following polysilicon deposition can have an adverse effect on the electrical properties of the SiO2/SiC interface. The primary effect is a negative shift in flatband voltage caused by an increase in fixed oxide charge and interface state density. These effects can be minimized or eliminated by restricting processing temperatures to 900 °C or below following polysilicon gate deposition.
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Xie et al. (1996) studied this question.
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