High-yield of memory elements from carbon nanotube field-effect transistors with atomic layer deposited gate dielectric

Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. We find that the memory effect can be controlled by carefully designing the gate dielectric in nm-thin layers. By using atomic layer depositions (ALD) of HfO 2 and TiO 2 in a triple-layer configuration, we achieve to our knowledge the first CNT FETs with consistent and narrowly distributed memory effects in their transfer characteristics. The study includes 94 CNT FET samples, providing a good basis for statistics on the hysteresis seen in five different CNT-gate configurations.