Answers are grounded in this paper and cite their sources.
In this paper, we propose a fully-integrated switch-capacitor (SC) dc-dc boost converter having high power efficiency, low output ripple, and high power density. It uses a switching scheme called nonoverlapped rotational time-interleaving (NORI) which eliminates shoot-through loss as well mitigates the adverse effect of dead times between successive charging and discharging phases which results into a small ripple. A basic cross-coupled voltage doubler has been adopted to implement the NORI scheme working over a wide range of switching frequencies. Dynamic adjustment of the frequency provides high power density as well as maintains high power efficiency over a wide load current range. The proposed converter has been fabricated in 0.18- μm CMOS thick gate process for 3.3 to 5.5 V conversion and output ripple not more than 0.5% of the output voltage. The converter uses only 440 pF to deliver up to 25 mA at 5.3 V regulated output. The measured peak power efficiency is 89% at 20 mA for unregulated output. With mixed mode regulations, the measured efficiency of the converter including analog blocks is 83.5% at 15 mA, while the overall efficiency is 75%. Power density of the designed converter is more than 0.85 W/mm2considering the capacitor area.
No takes yet. Share an insight, caveat, or question.
Das et al. (2014) studied this question.
Synapse has enriched 10 related papers. Consider them for comparative context: