Oscillation frequency in CML and ESCL ring oscillators

In this paper a model to accurately evaluate even in a pencil-and-paper manner the oscillation frequency of a ring oscillator made up by a CML or ESCL differential gate is proposed. The model allows us to simply estimate the oscillation frequency changes due both to the bias current change and to process tolerances. The model was validated by Spice simulations on both 6- and 20-GHz technologies for the CML ring oscillator, and on 0.8-/spl mu/m CMOS process for the ESCL ring oscillator. The estimated oscillation frequency agrees with the simulated one. Indeed, average errors lower than 10% were found.