MeV-energy As+ implantation into Si: Extended-defect reduction and planar n-p-n transistor fabrication

With 2.5 MeV-As+ implantation into Si, etch-pit density (after annealing) could be lowered below 104 cm−2, whether D was smaller than 5×10−4 or larger than 2×10−2. Here D stands for damage degree in the as-implanted sample [0(single-crystalline)≤D≤1 (amorphous)]. At given doses, D could be controlled to be at its optimal value by wafer temperature (over a range from 25–300 °C). By utilizing such MeV-energy implantation to form buried collector layers, planar n-p-n transistors could be successfully fabricated even without epitaxial growth.