Hardware decoder for turbo trellis‐coded modulations with higher‐order modulation schemes

This paper discusses the realization of a hardware decoder for turbo trellis‐coded modulation with high‐order modulation levels. In order to avoid an increase of decoding processing with the increase of modulation levels, a simplified decoding algorithm based on Max‐log MAP is considered, and a method for fast execution is proposed. When the proposed decoding procedure is used, the amount of computation can be reduced to approximately 1/25 of that by Max‐log MAP without degrading the performance (when the number of states in the element encoder is 8 and the number of input bits is 7). In order to realize the hardware decoder, the number of bits needed for each variable is analyzed. Then an efficient design procedure for the path metric module is presented. As an example of the design of a hardware decoder based on these investigations, the design of a turbo TCM decoder for 256QAM is presented.