If porous silicon (PSi) is going to be seriously considered for antireflection (AR) applications in the solar cell industry, it must not only offer superior AR properties, but must also prove minimally disruptive to the current manufacturing process. This limits its application to the final (backend) fabrication steps, after p–n junction formation. Since typical commercial junction depths are on the order of 350 nm, the PSi etching process must only consume a portion of this emitter layer if the electrical properties of these devices are to be maintained. In this study, we have focused on the development of a dynamic etching process to form thin (<120 nm) graded index PSi layers with excellent broadband AR properties.
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Striemer et al. (2003) studied this question.
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