Due to the scaling down of device geometry and increasing of frequency in deep submicron designs, crosstalk between interconnection wires has become an important issue in very large scale integration (VLSI) layout design. In this paper, we consider crosstalk avoidance during global routing. We present a global routing algorithm based on a new Steiner tree formulation and the Lagrangian relaxation technique. We also give theoretical results on the complexity of the problem.
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Zhou et al. (1999) studied this question.
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