Fpga Realization of Simplified Lte Turbo Decoder

This article presents a simplified turbo decoder using Max-Log-Maximum a posteriori algorithm and its hardware realization. This work adopted Very large-scale Integration Optimization techniques of parallel computation, pipeline process for minimizing computation complexity and computation latency in each soft-input-softoutput decoder. Also, three-stage pipeline process of decoder was proposed here to improve functional performance and to reduce the hardware memory requirement. Further, performance re-timing, resource sharing and area optimization have been applied in implementation of the proposed turbo decoder. The proposed design is synthesized and implemented on Zynq FPGA board. The analysis and study of efficient resource utilization of the proposed design has been done and the proposed design achieved high throughput and area reduction by 40 to 50% than conventional designs.