ATM switches—basic architectures and their performance

The prospect of a broadband ISDN based on the ATM principle has stimulated the development of new, high‐performance switching node architectures. In this paper different options for the switching networks used in such a node will be discussed in some detail. First, some generic architectures for the individual switching elements will be presented including the aspects of buffering and collision resolution, followed by a short classification of different types of switching networks and some performance figures for delta networks, a class of multi‐stage, single‐path interconnection networks. In the last section, the sensitivity of the performance results with respect to the traffic assumptions will be discussed.