Performance evaluation of double gate tunnel FET based chain of inverters and 6-T SRAM cell

In this work, a Lookup table based verilog-A model is employed in cadence to evaluate the performance of the chain of inverters and 6-T SRAM cell based on double gate Tunnel-field-effect transistor (DGTFET). In order to drive large capacitance with fixed number of inverters stages with constant width of N type DGTFET (W n ), it is found that the time delay performance of the inverter chain depends on the ratio of width of P type DGTFET of nth stage (Wp n ) to width of P type DGTFET of n-1th stage (Wp n−1 ). Simulation results investigated that the time delay is minimized to 0.265 ns for Wp n /Wp n−1 = 3. The impact of cell ratio (CR) and pull up ratio (PR) on the read stability and write ability of 6-T SRAM cell are investigated by using N curve simulations. It is observed that, increasing CR and PR strengthens the read stability and degrades the write ability of 6-T SRAM cell.