Potential Induced Degradation of Solar Cells and Panels

This paper is focusing on Potential Induced Degradation (PID) of wafer based standard p-type silicon technology once exposed to external potentials in the field. Test setups are presented for simulation of the PID in the lab and the influence of cell properties on PID is demonstrated in order to reveal the cell being the precondition for the PID. However, the solar cells need to be exposed to High Voltage Stress (HVS) caused by a negative potential relative to ground in order to potentially cause any relevant PID in the field within the 25 years life time of a solar panel. Besides the key parameters on cell level the paper is also presenting options on panel and system level in order to prevent PID and therefore to further decrease overall degradation rates of PV systems. Moreover, the impact of climatic conditions as temperature and humidity on the extent of PID was also investigated and results are presented in the paper.