Area efficient architectures for information integrity in cache memories

Information integrity in cache memories is a fundamen-tal requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it difficult to trade between the level of data in-tegrity and the chip area requirement. We focus on transient fault tolerance in primary cache memories and develop new architectural solutions to maximize fault coverage when the budgeted silicon area is not sufficient for the conventional configuration of an error checking code. The underlying idea is to exploit the corollary of reference locality in the organization and management of the code. A higher protec-tion priority is dynamically assigned to the portions of the cache that are more error-prone and have a higher prob-ability of access. The error-prone likelihood prediction is based on the access frequency. We evaluate the effective-ness of the proposed schemes using a trace-driven simula-tion combined with software error injection using four dif-ferent fault manifestation models. From the simulation re-sults, we show that for most benchmarks the proposed ar-chitectures are effective and area efficient for increasing the cache integrity under all four models. 1.