A multiprocessor-on-a-programmable-chip reconfigurable system for matrix operations with power-grid case studies

Recent advances in field–programmable gate array (FPGA) technologies have made feasible the implementation of low–cost parallel computing platforms for high–performance matrix computations. Compared to conventional multiprocessor systems, the resulting multiprocessors–on–a–programmable–chip (MPoPC) can provide unique advantages and opportunities in both software and hardware. It is shown in this paper that the performance of an MPoPC can be improved dramatically by adapting slightly intellectual property (IP)–based processing elements, and customising the memory and the interconnection network. The parallel LU factorisation of large, sparse doubly–bordered block diagonal (DBBD) matrices is employed as an application example. To enhance further the performance by software techniques, a run–time load balancing strategy for this algorithm is proposed and analysed. Extensive experimental results on benchmark matrices of size up to 7,917 × 7,917 for power networks demonstrate the effectiveness of our effort.