Analysis of postirradiation annealing of n-channel power vertical double-diffused metal–oxide–semiconductor transistors

The behavior of densities of the oxide trapped charge and the interface traps in gamma-ray irradiated n-channel power vertical double-diffused metal–oxide–semiconductor transistors during annealing at different temperatures and gate biases has been investigated. The experimental results have revealed the existence of a latent interface trap buildup (LITB) process. By use of numerical modeling, based on the hydrogen–water (H–W) model, the LITB process has been successfully simulated. The interface trap densities have been determined by both the midgap and the charge pumping methods, and the results have shown good qualitative agreement between these two methods. Isochronal annealing and switching bias experiments have also been performed. The experimental results are consistent with the H–W model.