A compact low noise operational amplifier for a 1.2 μm digital CMOS technology

A compact low noise operational amplifier using lateral p-n-p bipolar transistors in the input stage has been fabricated in a standard 1.2 /spl mu/m digital n-well CMOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p transistors exhibit low 1/f noise and good lateral /spl beta/. The fabricated op amp has an area of only 0.211 mm/sup 2/ with E/sub n/=3.2 nV//spl radic/(Hz), I/sub n/=0.73 pA//spl radic/(Hz), E/sub n/ and I/sub n/ 1/f noise corner frequencies less than 100 Hz, a -3 dB bandwidth greater than 10 MHz with a closed loop gain of 20.8 dB, a minimum PSRR (DC) of 68 dB, a CMRR (DC) of 100 dB, a minimum output slew rate of 39 V//spl mu/s, and a quiescent current of 2.1 mA at supply voltages of /spl plusmn/2.5 V. The operational amplifier drives a 1 k/spl Omega/ resistive load to 1 V peak-to-peak at 10 MHz and has been used as a versatile building block for mixed-signal IC designs.>