Prior reported PSPICE modeling work has demonstrated subnanosecond field rise-times for a head driven by an ideal current source. Results including the flexure interconnection have demonstrated 1 ns field rise-times without pulse distortion. Three write driver designs are explored. A simple H-bridge, an H-bridge with fly-over diodes, and an H-bridge with clamped transistors to improve switching speed are compared. The driver models are implemented using BJTs with state-of-the-art industry MOSIS process model parameters for PSPICE. The simulations show that for the low inductances considered and the relatively high supply voltage employed, the fly-over diodes are not required. The H-bridge with clamped transistors is the fastest driver (50 Ω resistive load) but suffers from a limited current capability for the small transistor areas required for high speed. The driver designs are restricted by termination requirements which generally do not correspond to optimum switching times for the 50 Ω resistive load used for preliminary evaluation. Finally, by reducing the interconnection length to 25 mm, stacking the head turns, and using the simple H-bridge driver, it is demonstrated that a field rise-time of less than 0.2 ns can be achieved. The resulting waveform is presented and the implications discussed.
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George et al. (2000) studied this question.
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