Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability

It is well known that reduced logic depth allows for operation at low voltages, therefore reducing power dissipation. However, such circuits are particularly susceptible to variations, which may compromise expected benefits. This brief presents a solution for low-power addition under variability, which successfully handles the challenge of increased threshold voltage variation. Specifically, we quantitatively compare the impact of variation on the performance of ripple-carry adder (RCA) and borrow-save adder (BSA), quantify the average power reduction achieved by BSA attained at low voltage values, at the cost of increased delay variation, and propose a technique that enhances BSA tolerance to variations. Using statistical timing evaluation at the 45-nm and 32-nm nodes, we estimate the maximum critical path delay variation and average power dissipation of BSA at different supply voltages. Our analysis reveals that BSA achieves three times smaller standard deviation of maximum delay than RCA at the same supply voltage. In addition, we show that it is possible to substantially reduce the supply voltage, decreasing by almost 60% the overall power dissipation of BSA in comparison to a counterpart operating at nominal voltage while keeping maximum delay less than that of RCA. Furthermore, simple design optimizations in the design of BSA are introduced that trade latency for variability, significantly reducing normalized standard deviation of the maximum delay.